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M39432
Single Chip 4 Mbit Flash Memory and 256 Kbit Parallel EEPROM
s
Multiple Memories on a Single Chip: - 4 Mbit Flash Memory (organised as 8 sectors) - 256 Kbit EEPROM - 64 Byte One Time Programmable Memory
s
CONCURRENT Mode (Read Flash while writing to EEPROM) WRITE, PROGRAM and ERASE Status Bits 2.7V to 3.6V Single Supply Voltage for PROGRAM, ERASE and READ Operations 100 ns Access Time (Flash and EEPROM blocks) Low Power Consumption - 60 A Stand-by mode (maximum) - Deep Power Down mode: 6 A (maximum), 200 nA (typical)
TSOP40 (NC) 10 x 20 mm
s s
s
s
s s s
Standard Flash Memory Package 100,000 Erase/Write Cycles (minimum) 10 Year Data Retention (minimum)
DESCRIPTION The M39432 is a single supply voltage memory device combining Flash memory and EEPROM on a single chip. The memory is mapped in two Table 1. Signal Names
A0-A18 DQ0-DQ7 EE EF G W R/B VCC VSS Address Inputs Data Inputs / Outputs
Figure 1. Logic Diagram
VCC
19 A0-A18 W
8 DQ0-DQ7
EEPROM Block Enable
EE
Flash Block Enable Output Enable Write Enable Ready/Busy Output Supply Voltage Ground
M39432 R/B
EF G
VSS
AI01946
November 1999
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Figure 2. TSOP Connections
NC NC A11 A9 A8 A13 A14 A17 W VCC A18 A16 A15 A12 A7 A6 A5 A4 NC NC 1 40 NC EE G A10 EF DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 R/B NC
10 11
M39432
31 30
The M39432 EEPROM block may be written bytewise or by a page at a time (up to 64 bytes). The integrity of the data can be secured with the help of the Software Data Protection (SDP). The M39432 Flash Memory block offers 8 sectors, each one 64 KByte in size. Each sector may be erased individually, and programmed a byte at a time. Each sector can be separately protected and unprotected against Program and Erase. Sector erasure may be suspended, while data is read from other sectors of the Flash memory block (or from the EEPROM block), and then resumed. The Flash memory block is functionally compatible with the M29W040 (4 Mbit Single Voltage Flash Memory). During a Program or Erase cycle in the Flash memory or during a Write cycle in the EEPROM, the status of the M39432 internal logic can be read on the Data Output pins DQ7, DQ6, DQ5 and DQ3. SIGNAL DESCRIPTION Address Inputs (A0-A18) The address inputs for the memory array are latched during a write operation. The EEPROM block is selected by the EE input, and the Flash memory block the EF input. A0-A14 access locations in the EEPROM block; A0-A18 access locations in the Flash memory block. When V ID (as specified in Table 11) is applied on the A9 address input, additional device-specific information can be accessed: - Read the Manufacturer identifier - Read the Flash block identifier - Read/Write the EEPROM block identifier - Verify the Flash Sector Protection Status.
20
21
AI01947
Note: 1. NC = Not Connected.
blocks: 4 Mbit of Flash memory and 256 Kbit of EEPROM. Each block operates independently during a Write cycle: in concurrent mode, the Flash Memory can be read while the EEPROM is being written. There is also a 64 byte row of OTP (one time programmable) EPROM.
Table 2. Absolute Maximum Ratings
Symbol TA TBIAS 1 TSTG 1 VIO 1,2 VCC 1 Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage Value -40 to 85 -50 to 125 -65 to 150 -0.6 to 7 -0.6 to 7 -0.6 to 13.5 Unit C C C V V V
VA9, VG, VEF 1,2 A9, G and EF Voltage
Note: 1. Stresses above those listed may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Please see the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum voltage may undershoot to -2 V, during transition and for less than 20 ns.
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Figure 3. Flash Block Sectors
A18 1 1 1 1 0 0 0 0
AI01362B
A17 1 1 0 0 1 1 0 0
A16 1 0 1 0 1 0 1 0 64K Bytes Block 64K Bytes Block 64K Bytes Block 64K Bytes Block 64K Bytes Block
TOP ADDRESS 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh
BOTTOM ADDRESS 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h
Data Input/Output (DQ0-DQ7) During a Write operation, one data byte is latched into the device when Write Enable (W) and one Chip Enable (EF or EE) are driven low. During a Read operation, the output presented on these pins is valid when Output Enable (G) and one Chip Enable (EF or EE) are driven low. The output is high impedance when the chip is deselected (both EE and EF driven high) or the outputs are disabled (G driven high). Read operations are used to output: - bytes in the Flash memory block - bytes in the EEPROM block - the Manufacturer Identifier - the Flash Sector Protection Status - the Flash Block Identifier - the EEPROM Identifier - the OTP row. Chip Enable (EE and EF) Each Chip Enable (EE or EF) causes the memory control logic, input buffers, decoders and sense amplifiers to be activated. When the EE input is driven high, the EEPROM memory block is not selected; when the EF input is driven high, the Flash memory block is not selected. Attempts to access both EEPROM and Flash blocks (EE low and EF low) are forbidden. Switching between the two chip enables (EE and EF) must not be made on the same clock cycle, a delay of greater than tEHFL must occur. The M39432 is in stand-by mode when both EF and EE are high (when no internal Erase or programming cycle is running). The power consumption is reduced to the stand-by level and
the outputs are held in the high state, independent of the Output Enable (G) or Write Enable (W) inputs. After 150 ns of inactivity, and when the addresses are driven at CMOS levels, the chip automatically enters a pseudo-stand-by mode. Power consumption is reduced to the CMOS stand-by level, while the outputs continue to drive the bus. Output Enable (G) The Output Enable gates the outputs through the data buffers during a Read operation. The data outputs are left floating in their high impedance state when the Output Enable (G) is high. During Sector Protect (Figure 8) and Sector Unprotect (Figure 9) operations (for the Flash memory block only), the G input must be held at VID (as specified in Table 11). Write Enable (W) Addresses are latched on the falling edge of W, and Data Inputs are latched on the rising edge of W. Ready/Busy (R/B) When the EEPROM block is engaged in an internal Write cycle, the Ready/Busy output shows the status of the device: - R/B is 0 when a Write cycle is in progress - R/B is Hi-Z when no Write cycle is in progress The Ready/Busy pin does not show the status of a Program or Erase cycle in the Flash memory. This pin can be used to show the status of the EEPROM block, even when reading data (or fetching instructions) from the Flash memory block.
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Table 3. Operations
Operation Read VIH VIL Write VIH VIL Output Disable VIH Stand-by
Note: 1. X = VIH or VIL.
EF VIL
EE VIH VIL VIH VIL VIH VIL VIH
G VIL
W VIH
DQ0 - DQ7 Read from Flash Block Read from EEPROM Block Write to Flash Block
VIH
VIL Write to EEPROM Block
VIH X
X X
Hi-Z Hi-Z
VIH
This open drain output can be wire-ORed, using an external pull-up resistor, when several M39xxx devices are used together. VCC Supply Voltage The V CC Supply Voltage supplies the power for the device. The M39432 cannot be written when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and during power surges. A 100 nF capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin, to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VSS Ground The V SS Ground is the reference for all voltage measurements. DEVICE OPERATION The M39432 memory device is addressed via 19 inputs (A0-A18) and carries data on 8 Data Inputs/ Outputs (DQ0-DQ7). There are four other control inputs: Chip Enable EEPROM (EE), Chip Enable Flash Memory (EF), Output Enable (E) and Write Enable (W). The Chip Enable inputs (EF or EE) are used mainly for power control (turning the chip on and off) and for block selection (selecting the EEPROM block or the Flash memory block). The gating of data to the DQ0-DQ7 pins should be controlled using the Output Enable input (G). The permitted operating modes of the device are listed in Table 3. Read For a Read operation, the Output Enable (G) and one Chip Enable (EF or EE) must be driven low.
As noted on the previous page, Read operations are used to read the contents of: - bytes in the Flash memory block - bytes in the EEPROM block - the Manufacturer Identifier - the Flash Sector Protection Status - the Flash Block Identifier - the EEPROM Identifier - the OTP row. The instruction sequences for selecting between these areas is summarized in Table 4. Write Writing data requires: - a Chip Enable (either EE or EF) to be low - the Write Enable (W) to be low and the Output Enable (G) to be high. Addresses in the Flash memory block (or the EEPROM block) are latched on the falling edge of W or EF (or EE) whichever occurs the later. The data to be written to the Flash memory block (or EEPROM block) is latched on the rising edge of W or EF (or EE) whichever occurs first. The Write operation is used in two contexts: - to write data to the EEPROM memory block - to enter the sequence of bytes that makes up one of the instructions shown in Table 4. The programming of a byte of Flash memory involves one of these instructions (as described in the section entitled "Instructions" on this page). Specific Read and Write Operations Device specific information includes the following: - Read the Manufacturer Identifier - Read the Device Identifier - Define the Flash Sector Protection - Read the EEPROM Identifier - Write the EEPROM Identifier
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Table 4. Instructions 1
Instruction Read Manufacturer Identifier 2 Read Flash Identifier 2 Read OTP Row Read Sector Protection Status2 Program a Byte of Flash Memory Erase a Sector of Flash Memory Erase the Whole of Flash Memory Suspend Sector Erase Resume Sector Erase EEPROM Power Down Deep Power Down SDP Enable (EEPROM) SDP Disable (EEPROM) Write OTP Row Return (from OTP Read or EEPROM Power Down) Reset EE EF 1 0 Cycle 1 AAh @5555h AAh @5555h AAh @5555h AAh @5555h AAh @5555h AAh @5555h AAh @5555h B0h @any address 30h @any address AAh @5555h 20h @5555h AAh @5555h AAh @5555h AAh @5555h F0h @any address AAh @5555h F0h @any address 55h @2AAAh F0h @any address 55h @2AAAh 55h @2AAAh 55h @2AAAh A0h @5555h 80h @5555h B0h @5555h Write Byte 1 AAh @5555h Write Byte 1 Write Byte 2 55h @2AAAh Write Byte 2 20h @5555h Write Byte N Write Byte N 55h @2AAAh 30h @5555h Cycle 2 55h @2AAAh 55h @2AAAh 55h @2AAAh 55h @2AAAh 55h @2AAAh 55h @2AAAh 55h @2AAAh Cycle 3 90h @5555h 90h @5555h 90h @5555h 90h @5555h A0h @5555h 80h @5555h 80h @5555h Cycle 4 Read Identifier with (A0,A1,A6) set to (0,0,0) Read Identifier with (A0,A1,A6) set to (1,0,0) Read Byte 1 Read Identifier with (A0,A1,A6) set to (0,1,0) Data @ Address AAh @5555h AAh @5555h 30h 55h @ Sector @2AAAh address 55h @2AAAh 10h @5555h 30h @ Sector address3 Read Byte 2 Read Byte N Cycle 5 Cycle 6 Cycle 7
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0 1 0 0 0
1 0 1 1 1
0
1
1
0
Reset (short instruction)
1
0
Note: 1. AAh @ 5555h means "Write the value AAh at the address 5555h". 2. This instruction can also be performed as a Verify operation with A9=VID (please see the section entitled "Flash Sector Protection and Unprotection" on page 18). 3. Addresses of additional sectors to be erased must be entered within a time-out of 80 s of each other.
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Table 5. Device Identifier Operations
Instruction Read Manufacturer Identifier Read Flash Block Identifier Read EEPROM Block Identifier
Note: 1. X = Don't Care.
EF VIL VIL VIH
EE VIH VIH VIL
G VIL VIL VIL
W VIH VIH VIH
A0 VIL VIH X
A1 VIL VIL X
A6 VIL VIL VIL
A9 VID VID VID
Other Address Lines Don't Care Don't Care Don't Care
DQ0 - DQ7 20h 0E3h 64 userdefined bytes
To access these, A9 is held at V ID (as specified in Table 11) and the specific logic levels, shown in Table 5, are applied to the address inputs A0, A1 and A6. The OTP row is accessed with a specific software sequence, as described in the section entitled "Writing the OTP Row" on page 11. Instructions Instructions consist of a sequence of specific Write operations, as summarized in Table 4. The time between two consecutive bytes must be shorter than the time-out value (tWLWL). Each received byte is decoded sequentially, and not executed as a standard Write operation. The overall instruction is executed when the correct number of bytes have been properly received. The sequence must be followed exactly. If an invalid combination of instruction bytes occurs, or time-out between two consecutive bytes, the device logic resets itself to the Read state, when addressing the Flash block, or is directly decoded as a single operation, when addressing the EEPROM block. The M39432 instructions set, as summarized in Table 4, includes: s Program a byte in the Flash memory block
s s
- Write the whole OTP row (once) - Read from the OTP row
s s
Reset and Return Read identifiers: - Read the Manufacturer Identifier - Read the Flash Block Identifier
For efficiency, each instruction consists of a twobyte escape sequence, followed by a command byte or a confirmation byte. The escape sequence consists of writing the value AAh at address 5555h, in the first cycle, and the value 55h at address 2AAAh, in the second cycle. In the case of the Erase instructions, an additional escape sequence is required, for final confirmation that the instruction is the intended one. POWER SUPPLY AND CURRENT CONSUMPTION Power Up The M39432 internal logic is reset, to Read mode, upon a power-up event. All Write operations to the EEPROM are inhibited for the first 5 ms. No new Write cycles can be started when VCC is below VLKO (as specified in Table 11). However, for maximum security of the contents of the memory, and to remove the possibility of a byte being written on the first rising edge of EF, EE or W, at least one of EF, EE or W should be tied to VIH during the power-up process. Stand-by When both EE and EF are high, the memory enters Stand-by mode, and the Data Input/Output pins are placed in the high-impedance state. To reduce the Supply Current to the Stand-by Supply Current, EE and EF should be held within VCC0.2V. If the Stand-by mode is set during a Program or Erase cycle, the memory continues to use the Supply Current until the cycle is complete.
Read the Protection Status of a Flash Sector Erase instructions: - Flash Sector Erase - Flash Block Erase - Flash Sector Erase Suspend - Flash Sector Erase Resume
s s s
EEPROM Power Down Deep Power Down Change the EEPROM software write protection: - Enable SDP - Disable SDP
s
OTP row access:
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Table 6. Status Bits
EF Flash VIL EE VIH DQ7 Data Polling Data Polling DQ6 Toggle Flag Toggle Flag DQ5 Error Flag X DQ4 X DQ3 Erase TimeOut X DQ2 X DQ1 X DQ0 X
EEPROM
VIH
VIL
X
X
X
X
Note: 1. X = Not a guaranteed value, can be read either as `1' or `0'.
Automatic Stand-by If CMOS levels (VCC0.2V) are used to drive the bus, and the bus is inactive for more than 150 ns, the memory enters the Automatic Stand-by state. The internal supply current is reduced to the Stand-by Supply Current, ICC3. Deep Power Down The ICC consumption mode can be reduced to a minimum using the Deep Power Down instruction (as shown in Table 4). The device is set in a sleep mode until the next Reset instruction is executed. EEPROM Power Down The M39432 can power-down the EEPROM block using the specific instruction shown in Table 4. Once in this state, the EEPROM block is no longer accessible, until a Return instruction is executed. READ Read operations and instructions can be used: - to read the contents of the memory array (Flash memory block or EEPROM block) - to read the memory array status and identifiers (Flash memory block or EEPROM block). Read Data (from Flash Memory or EEPROM) For a Read operation, the Output Enable (G) and one Chip Enable (EF or EE) must be driven low. Read the Manufacturer Identifier There are two alternative methods for reading the Manufacturer Identifier: using a Read operation or using a Read instruction. Read Operation. The Manufacturer Identifier can be read with a Read operation by applying V ID (as specified in Table 11) on A9, and the logic levels specified in Table 5 applied to A0, A1, A6. Read Instruction. The Manufacturer Identifier can also be read using an instruction composed of four operations: three specific Write operations (as specified in Table 4) and a Read operation. This either accesses the Manufacturer Identifier, the Flash Block Identifier or the Flash Sector Protection Status, depending on the levels that are being applied to A0, A1, A6, A16, A17 and A18.
Read the Flash Block Identifier Similarly, there are two alternative methods for reading the Flash Block Identifier (E3h): using a Read operation or using a Read instruction. Please see the previous section, entitled "Read the Manufacturer Identifier", and Table 5 and Table 4 for details. Read the EEPROM Block Identifier The EEPROM Block Identifier (64 bytes, user defined) can be read with a single Read operation by holding A6 low and A9 at VID (see Table 5). Read the OTP Row The OTP row is mapped in the EEPROM block. With EE held low, and EF held high, an EEPROM Read instruction is composed, as specified in
Figure 4. Data Polling Flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO
YES
DQ5 =1 YES READ DQ7
DQ7 = DATA NO FAIL
YES
PASS
AI01369B
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Table 4. This consists of the writing of three specific data bytes at three specific memory locations (each location on a different page) as a prefix to reading the OTP row content. When accessing the OTP row, only the least significant bits of the address bus (A0 to A6) are decoded (of which A6 must be low). Each Read of the OTP row has to be followed by the Return instruction (as shown in Table 4). Read the Flash Sector Protection Status There are two alternative methods for reading the Flash Sector Protection Status: using a Verify operation with A9=V ID (as described on page 18) or using a Read instruction as described in the section entitled "Read the Manufacturer Identifier", starting on page 7. Using the Read instruction, the logic levels on A0, A1, A6 select the correct instruction, while A16, A17 and A18 specify which sector is being addressed. This returns the value 01h if the Flash sector is protected, and the value 00h if the Flash sector is not protected. Read the Status Bits The latency period of Write, Erase and Program cycles can be monitored by the application software, by using the M39432 status bits. The Ready/Busy pin provides the status information during a write cycle to the EEPROM block (though not to the Flash memory block). An internal status register carries the status information during a programming or erase cycle. A Read operation, during the program or write cycle, causes the contents of this register to be presented to the I/O ports (DQ0-DQ7), as summarized in Table 6. Data Polling flag, DQ7. The I/O lines (DQ0DQ7) are first used as inputs, carrying the data that is to be written to the EEPROM or programmed in the Flash memory. Once the Write or Program cycle is underway, these lines become outputs (and can be read using a normal Read operation). The value presented on DQ7 is the inverse of the data bit that was presented by the user. When the cycle is complete, the lines remain as outputs, and the value that is presented on DQ7 is the non-inverted value that was originally specified for writing. The suitable algorithm for using this method of polling is shown in Figure 4. When a Write or Program cycle is in progress, data bit DQ7 is set to the complement of the original data bit 7 (or to `0' in the case of an Erase cycle in the Flash memory block). When DQ7 is identical to the old data (or to `1' in the case of an Erase cycle in the Flash memory block) and the Error bit (DQ5) is still '0', the cycle is complete. For the flash memory block, data Polling is effective after the fourth pulse on the W line for
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Figure 5. Data Toggle Flowchart
START
READ DQ5 & DQ6
DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ6
DQ6 = TOGGLE YES FAIL
NO
PASS
AI01370
Program cycles, and after the sixth pulse on the W line for Erase cycles. The Data Polling Read instruction must address the same location as the byte that is being programmed, or within the same Flash sector as the one that is being erased. Toggle flag, DQ6. During an internal Write, Program or Erase cycle, DQ6 toggles between '0' and '1', on successive Read accesses to any byte of the memory (when either G, EE or EF is held low). When the internal cycle is complete, the toggling is stopped, and the data read on DQ0-DQ7 is that of the addressed memory byte. A subsequent Reading at the same address will result in the same data being read. This alternative method for detecting when the internal Write, Program or Erase cycle has completed, is shown in the flowchart in Figure 5. When an internal cycle is in progress, data bit DQ6 toggles between `1' and `0' for successive Read operations. When DQ6 no longer toggles and the Error bit DQ5 is '0', the operation is complete. To determine if DQ6 has toggled, each poll requires two consecutive Read operations to see if the data read is the same each time. For the flash memory block, data Toggling is effective after the fourth pulse on the W line for
M39432
Table 7. Summary of the Use of Status Bits
Operation Program (Flash) or Erase (EEPROM) Program Error (Flash) Flash Block Erase Sector Erase Sector Erase before Time-Out Address DQ7 (Data Polling Bit) DQ7 DQ6 (Toggle Bit) DQ5 (Program Error Bit) 0 DQ3 (Erase Time-Out Bit) X
Any address Any address in the Flash block Any address in the Flash block Sector address to be erased Sector address to be erased Any byte in the sector in erase mode Other sector addresses
Toggling
DQ7 01 01 01
Toggling Toggling 2 Toggling 2 Toggling 2
1 0 0 0
X 1 1 0
Invalid data on DQ7-DQ0 DQ6 toggles for 15 s, then behaves as for a standard Read operaion 01 Toggling 2 1 1
Erase Suspend
Erase Error
Sector address
Note: 1. If all the sectors to be erased are protected, DQ7 is reset to 0 for about 100 s, then returns to the state it was in for the previously addressed byte. No erasure is performed. 2. If all the sectors to be erased are protected, DQ6 is reset to 0 for about 100 s, then returns to the state it was in for the previously addressed byte. No erasure is performed.
Figure 6. EEPROM SDP-Enable Flowcharts
SDP Set SDP not Set
Write AAh in Address 5555h
Write AAh in Address 5555h
Page Write Timing
Write 55h in Address 2AAAh Page Write Timing
Write 55h in Address 2AAAh
Write A0h in Address 5555h
Write A0h in Address 5555h Write is enabled
SDP is set
Write Data to be Written in any Address
SDP ENABLE ALGORITHM
Write in Memory
Write Data and SDP Set after tWC
AI01698C
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Program cycles, and after the sixth pulse on the W line for Erase cycles. Error flag, DQ5 (Flash memory block only). This bit is set to '1' when there is a failure during a Program, Sector Erase, or the Bulk Erase instruction in the Flash memory block. Otherwise, the bit is held at `0'. If an error occurs during a Program or Sector Erase instruction, the sector in which the error occurred, must not be used any more. Other sectors may still be used, though. The Error bit is reset after a Reset instruction. If DQ5 becomes set to '1' during either of the polling algorithm, shown in Figure 4 and Figure 5, DQ7 (DQ6) should be checked again in case it had changed simultaneously with DQ5. If DQ7 shows the original data bit (after a Program cycle) or if DQ7 is set to '1' (after an Erase cycle), or if DQ6 has ceased to toggle, the operation is successful and the calling routine can resume normal execution. It is recommended, as a final check, that a second Read be performed, and that the read value be compared against the original data (in the case of a Write or Program cycle) or against the value FFh (in the case of an Erase cycle). If the comparison shows false, this should be flagged as an error. Erase Time-Out Bit (DQ3). The Erase Time-Out Bit can be used to identify the start of the internal controller operation during a Sector Erase cycle. While the sector addresses (after cycle 5 in Table 4) are being supplied at a faster rate than one every 80 s between two sector addresses, the M39432 holds the DQ3 bit at 0. This indicates that additional sectors can still be added to the list of sectors that are to be erased. Once the internal controller starts erasing, the Erase Timer Bit is set to `1'. BYTE WRITE (OR PAGE WRITE) IN EEPROM Writing a byte, or a page of bytes, to the EEPROM block is performed as an operation (see Table 3). This is as opposed to Programming a byte in the Flash memory, which is performed as an instruction (see Table 4). Byte Write in the EEPROM Block A write operation is initiated when EE is taken low, while EF is kept high, the Write Enable (W) is taken low, and the output enable (G) is held high. Addresses are latched on the falling edge of W or EE (whichever occurs the later). Figure 7. EEPROM SDP-Disable Flowchart
Write AAh in Address 5555h
Write 55h in Address 2AAAh
Page Write Timing
Write 80h in Address 5555h
Write AAh in Address 5555h
Write 55h in Address 2AAAh
Write 20h in Address 5555h
Unprotected State after tWC (Write Cycle time)
AI01699C
Once initiated, the Write operation continues under internal timing, until it is completed. This period (tWHRH) is specified in Table 16. The status of the Write operation is indicated on the Data Polling and Toggle bits (as described on the previous page), and on the Ready/Busy output (which is driven low for the duration of the internal Write cycle). Page Write in the EEPROM Block The Page Write mode allows up to 64 bytes to be written on a single page in a single go. This is achieved through a series of successive Write operations, no two of which are separated by more than the tWLWL value (as specified in Table 16). The page write is initiated as a byte write operation: following the first Byte Write instruction, the host may send another address and data with a minimum data transfer rate of: 1/t WLWL. The internal write cycle can start at any instant after tWLWL. Once initiated, the write operation is internally timed, and continues, uninterrupted, until completion.
Table 8. Write the EEPROM Block Identifier
EF VIH EE VIL G VIH W VIL A6 VIL A9 VID Other Address Lines Don't Care DQ0 - DQ7 64 user-defined bytes
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M39432
All bytes must be located on the same page address (A6-A18 must be the same for all bytes). Otherwise, the Page Write operation is not executed. As with the single byte Write operation, described above, the DQ6 and DQ7 lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle. EEPROM Block Software Data Protection The Software Data Protection (SDP) instruction protects the EEPROM block from inadvertent Write operations, for example that might be caused under uncontrolled bus conditions. By default, the M39432 is shipped in the unprotected state: the EEPROM memory can be written to normally. After the SDP Enable instruction, the device enters the Protected Mode, and further write operations have no effect on the EEPROM contents. The device remains in this mode until a valid SDP Disable instruction has been received. The device then returns to its unprotected state. To enable the Software Data Protection, the device has to be written (under Page Write timing conditions) with three specific data bytes at three specific memory locations (each location on a different page) as shown in Table 4 and Figure 6. Figure 6 shows that there are three ways to use the SDP-Enable instruction. Firstly, as shown in the flow-chart on the left, it can be used as a threebyte instruction that sets the SDP. Secondly, it can be used as a way of writing data to the EEPROM even when the SDP is set. Only if the data to be written is preceeded by the correct three byte instruction, and all the bytes are written with the correct Page Write timing, will the request be accepted, and acted on. Lastly, if the SDP is currently not set, the instruction can be used as a means of performing a Page Write, and setting the SDP at the same time. To disable the Software Data Protection the user has to write specific data bytes into six different locations (under Page Write timing conditions) with different bytes being written on different pages, as shown in Figure 7. The Software Data Protection state is held internally in a non-volatile latch (and so the state is remembered across power-on and power-off events. Access to this latch, through the SDP Enable and Disable instructions, require the same write time (tWC) as for the non-volatile memory. This Write operation can be monitored on the Toggle bit (status bit DQ6) and the Ready/Busy pin, but not on DQ7. The Ready/Busy output is driven low from the first written byte (the first Write AAh,@5555h of the SDP sequence) until the completion of the internal Page Write sequence. Writing the OTP Row Writing in the OTP row is enabled by an instruction composed of three specific Write operations, under Page Write timing conditions, as shown in Table 4. These instructions write data bytes at three specific memory locations, each location on a different page, followed by the data (between 1 and 64 bytes) that is to be stored in the OTP row. This action can only be performed once. Even by writing fewer than all 64 bytes on the first write to the OTP row, none of the bytes, including any that have not yet been changed, can be modified at a later time. When accessing the OTP row, the only least significant address bits (A0 to A6) are decoded. Of these, A6 must be held at 0. Writing the EEPROM Block Identifier The EEPROM Block Identifier (64 bytes) can be written with a single Write operation with VID applied on A9, and A6 is driven low, as shown in Table 8. Programming the Flash Block Programming a byte in the Flash memory block is performed using the instruction shown in Table 4. This is different to writing data to the EEPROM block, which is performed as an operation (as shown in Table 3). Similarly, an instruction is needed when erasing a sector of Flash memory. The Program instruction is a sequence of three specific Write operations, followed by a Write operation bearing the address and data that is to be written (as shown in Table 4). The M39432 automatically starts and performs the programming after the fourth write operation. In this way, the Flash memory block can be programmed a byte at a time. The Flash memory block rejects any further instructions that arrive during the execution of the Program instruction. During programming, the memory status may be checked by reading the status bits DQ7, DQ6 and DQ5, as described on page 8. Data Polling using DQ7. Please see the description on page 8. Data Toggling using DQ6. Please see the description on page 8. Flash Block Erase A Write to the EEPROM block is an operation that triggers an automatic, internal sequence of Byte Erase followed by Byte Write. The Flash memory block, though, is different. Writing to the Flash memory block first requires an explicit Erase operation. The Flash memory Erase instruction cannot be addressed to a byte at a time. The Erase can only
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M39432
Figure 8. Sector Protection Flowchart
START
SECTOR ADDRESS on A16, A17, A18 EE = VIH
n=0
G, A9 = VID, EF = VIL
Wait 4s W = VIL Wait 100s W = VIH G = VIH Wait 4s
Verify Sector Protection Status1
DQ0 =1 YES A9 = VIH PASS
NO
++n = 25 YES A9 = VIH FAIL
NO
AI01948C
Note: 1. The Verify Sector Protection Status operation is specified in Table 9.
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M39432
Table 9. Flash Sector Protection
EF VIL VIL EE VIH VIH G VID VIL W VIL VIH A0 X VIL A1 X VIH A6 X VIL A9 VID VID A12 X X A16 SA SA A17 SA SA A18 SA SA DQ0 - DQ7 Protection Activation Verify Sector Protection Status: when DQ0=1, the sector is protected
Note: 1. X = Don't Care 2. SA = Sector address
be addressed to a whole sector. Either one sector (or more) can be explicitly selected for erasure, or the Bulk Erase instruction can be used to erase all the sectors in the Flash memory block. During an Erase cycle, the memory status may be checked by reading the status bits DQ7, DQ6 and DQ5, as described on page 8. The Error bit (DQ5) returns a '1' if there has been an Erase Failure (if the maximum number of Erase cycles has been exceeded). The Program instruction to a byte in the Flash memory block is ignored if it is in a protected sector. Similarly, the Bulk Erase instruction is ignored if all the Flash memory sectors are protected. If all the addressed sectors, for an Erase instruction, are protected, nothing is erased. DQ7 and DQ6 are set to '0' for about 100 s, and then are returned to their values from the previously addressed byte. Bulk Erase Instruction. The Bulk Erase instruction uses six Write operations followed by a number of Read operations, to read the status register bits. This is summarized in Table 4. If any part of the Bulk Erase instruction sequence is wrong, the device reverts to being in its Read mode for the Flash memory, and does not execute the erase instruction. The M39432 rejects any further instructions that arrive during the execution of the Bulk Erase instruction. Sector Erase Instruction. The Sector Erase instruction uses six Write operations to specify the first sector that is to be erased, and an additional
Write operation for each additional sector that is to be erased in parallel with the first. This is summarized in Table 4. These Write operations are transmitted under normal Page Write timing conditions. The status of the internal timer can be monitored on DQ3 (Erase Time-Out bit) as described on page 10. If DQ3 is '0' the Sector Erase instruction has been received and the timer is counting. If DQ3 is '1', the time-out has expired, and the M39432 is either in the process of erasing, or has finished (as indicated on DQ7 and DQ6). Any instruction arriving before the expiration of the Erase Time-Out period, other than Erase Suspend or Erase Resume instruction, aborts the Erase instruction, and resets the device in its read Flash memory mode. During the execution of the Erase instruction, the Flash memory block accepts only Reset and Erase Suspend instructions. Erase Suspend Instruction. When a Sector Erase cycle is in progress, the Erase Suspend instruction can be used to suspend the cycle. This allows the reading of data from another Flash sector while the Sector Erase instruction is on hold. This instruction involves writing B0h at any address (as shown in Table 4). Erase Suspend is accepted only during the Sector Erase instruction execution, and defaults to the Read Flash memory mode, otherwise. An Erase Suspend instruction executed during an Erase Time-Out will, in addition to suspending the Erase, terminate the time-out period.
Table 10. Flash Unprotection (all sectors)
EF VID VIL EE VIH VIH G VID VIL W VIL VIH A0 X VIL A1 X VIH A6 X VIH A9 VID VID A12 VIH X A16 VIH SA A17 X SA A18 X SA DQ0 - DQ7 Activation of Unprotected mode Verify Sector Protection Status: when 00h, the sector is unprotected
Note: 1. X = Don't Care 2. SA = Sector address
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M39432
Figure 9. Sector Unprotecting Flowchart
START EE = EF = VIH n=0 A18, A17, A16 = VIH A12, A9, A6, G = VIH
Wait 4s
EF, G, A9 = VID Wait 4s W = VIL Wait 10ms W = VIH EF, G = VIH Wait 4s
Verify Sector Protection Status1,2
Previous Sector (Decrement A18, A17, A16)
NO
DQ0-7 = 00h
YES
NO
++n = 1000 YES FAIL
Last Sector YES PASS
NO
AI01949C
Note: 1. The Verify Sector Status operation is specified in Table 10. 2. A6 is kept at VIH during unprotection algorithm in order to secure best unprotection verification. During all other protection status reads, A6 must be kept at V IL.
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M39432
Table 11. DC Characteristics (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
Symbol ILI ILO ICC11 ICC2 ICC3 ICC4 ICC5 ICC6 VIL VIH VOL VOH VID IID VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Read Flash) TTL Supply Current (Read EEPROM) TTL Supply Current (Stand-by) CMOS Supply Current (Flash block Program or Erase) Supply Current (EEPROM Write) Supply Current in Deep Power Down Mode Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 High Voltage VID Current VCC minimum for Write, Erase and Program A9 = VID 1.9 IOL = 1.8 mA IOH = -100 A VCC - 0.4 11.5 12.5 50 2.2 Test Condition 0 V VIN VCC 0 V VOUT VCC (EE,EF,G) = (VIH,VIL,VIH), f = 6 MHz (EE,EF,G) = (VIL,VIH,VIH), f = 6 MHz EF = EE = VCC 0.2 V Byte program, Sector or Chip Erase in progress During tWC After a Deep Power Down instruction (see Table 4) -0.5 2 3 3 0.2 3 3 Min. Mean2 (Typ.) Max. 1 1 15 15 60 20 20 6 0.8 VCC + 0.5 0.45 Unit A A mA mA A mA mA A V V V V V A V
Note: 1. When reading the Flash block and an EEPROM write cycle is already underway, the supply current is I CC1 + ICC5. 2. Averaged (over time) typical value.
Table 12. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages 10 ns 0.45 V to 2.4 V 0.8 V and 2 V 1.5 V
Figure 11. Output AC Testing Load Circuit
VCC IOL 1N914 Device Under Test 1N914 IOH CL = 30pF
Figure 10. AC Testing Input Output Waveforms
2.4V 1.5V 0.45V
AI01950
CL includes JIG capacitance VOUT = 1.5V when the Device Under Test is in the Hi-Z output state.
AI01951C
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M39432
Table 13. Read Mode AC Characteristics (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
M39432 Symbol Alt. Parameter Test Condition -100 Min Address Valid to Next Address Valid (EE,EF,G) = (VIL,VIH,VIL) or (EE,EF,G) = (VIH,VIL,VIL) (EE,EF,G) = (VIL,VIH,VIL) or (EE,EF,G) = (VIH,VIL,VIL) G = VIL G = VIL (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL) (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL) G = VIL G = VIL (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL) (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL) (EE,EF,G) = (VIL,VIH,VIL) or (EE,EF,G) = (VIH,VIL,VIL) 0 30 0 100 Max -120 Min Max -150 Min Max Unit
tAVAV
tRC
100
120
150
ns
tAVQV
Access Time: Address Valid tACC to Output Valid Chip Enable Low to Output Transition Access Time: Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z
100
120
150
ns
tELQX1 tELQV2 tGLQX1
tLZ tCE
0 120
0 150
ns ns
tOLZ
0
0
0
ns
tGLQV2
tOE
40
55
55
ns
tEHQX tEHQZ1
tOH tHZ
0 40
0 40
ns ns
tGHQX
tOH
0
0
0
ns
tGHQZ1
tDF
30
40
40
ns
tAXQX
tOH
Address Transition to Output Transition EE Active to EF Active or EF Active to EE Active
0
0
0
ns
tEHFL
tCED
100
100
100
ns
Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of EE (or EF) without increasing tELQV.
Table 14. Input and Output Parameters 1 (TA = 25 C, f = 1 MHz)
Symbol CIN COUT Input Capacitance Output Capacitance Parameter Test Condition VIN = 0V VOUT = 0V Min. Max. 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
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tAVAV VALID tAVQV tEHFL tAXQX
A0-A18
EE (EF) tELQV
tEHFL
EF (EE) tEHQZ tEHQX tELQX
G tGLQV tGLQX VALID tGHQX tGHQZ
Figure 12. Read Mode AC Waveforms (with Write Enable, W, high)
DQ0-DQ7
OUTPUT ENABLE
DATA VALID
AI01952
ADDRESS VALID AND CHIP ENABLE
M39432
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M39432
Figure 13. Write Mode AC Waveforms (W controlled)
WRITE CYCLE A0-A18 VALID tWLAX tAVWL E
(1)
tWHEH
tELWL G tGHWL W tWLWH
tWHGL
tWHWL tDVWH DQ0-DQ7 VALID tWHRH RB tWHRL VCC tVCHEL
AI01953
tWHDX
Note: 1. E signifies EF when EE = VIH, and it signifies EE when EF = VIH . 2. Addresses are latched on the falling edge of W, Data are latched on the rising edge of W.
The Toggle bit (DQ6) stops toggling when the Erase cycle is suspended. The Toggle bit status must be monitored using an address that is not in the Flash sector being erased. DQ6 will stop toggling within 15 s of the Erase Suspend instruction having been sent. The M39432 will then be set automatically into Read Flash Memory mode. When an Erase cycle is suspended, reading from the Flash sectors that were being erased will return invalid data. Reading is valid from any Flash sectors that are not being erased. During an Erase Suspend cycle, the Flash memory responds only to Erase Resume and Reset instructions. A Reset instruction will definitively abort the erase cycle, and can leave invalid data in the Flash sectors that was being erased. Erase Resume Instruction. If an Erase Suspend instruction was the last to have been executed, this instruction allows the Erase cycle to be resumed. The Erase Resume instruction involves writing 30h to any address (as shown in Table 4).
Flash Sector Protection and Unprotection Each Flash sector can be individually protected against Program or Erase instructions. This mode is activated when both A9 and G are set to VID (specified in Table 11) and the Flash sector address is applied on A16, A17 and A18, as shown in Figure 8 and Table 9. Flash Sector Protection is programmed with the help of a specific sequence of levels applied on the EF, EE, G, A0, A1, A6, A9, A16, A17 and A18 lines, as shown in Table 9. Any attempt to Program or Erase a protected Flash sector is ignored by the device. Flash sectors can be unprotected, to allow the subsequent updating of their contents. The Sector Unprotection operation unprotects all sectors together (from sector 0 up to sector 7). The Flash Sector Unprotection operation is invoked by applying the specific levels on the EF, EE, G, A0, A1, A6, A9, A12, A16, A17 and A18 lines, as shown in Table 10. Verification of the protection status can be obtained after each new sector has been protected, or after all sectors have been
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M39432
Figure 14. Write Mode AC Waveforms (EE or EF controlled)
WRITE CYCLE A0-A18 VALID tELAX tAVEL W tWLEL G tGHEL E (1) tEHEL tDVEH DQ0-DQ7 VALID tWHRL RB tEHDX tELEH tEHGL tEHWH
VCC tVCHWL
Note: 1. E signifies EF when EE = VIH, and it signifies EE when EF = VIH . 2. Addresses are latched on the falling edge of E, Data are latched on the rising edge of E.
AI01954
unprotected. Following the protection of a new sector, the status is found on DQ0 as shown by the sequence in Figure 8. Following the unprotection of all sectors, the status is found on DQ0-DQ7 as shown by the sequence in Figure 9. These two Verify Sector Protection Status operations are implemented like Read operations, but provide a more severe test of the correct functioning of the device than does a Read Sector Protection instruction (as shown in Table 4). Reset Instruction Reset is an instruction involving either one write operation or three write operations (as shown in Table 4). The Reset instruction returns the memory to its Read mode, and resets any errors in the Status Register. If the Reset instruction is issued during a Sector Erase cycle, or during a Programming cycle, then the internal logic will take up to 10 s to abort. During the abort period, no valid data can be read from the memory. Issuing a Reset command during a sector Erase cycle will leave invalid data in the memory.
GLOSSARY Block: Flash memory block (4 Mbit) or EEPROM block (256 Kbit) Bulk: the whole Flash memory block (4 Mbit) Sector: 64 KByte of Flash memory Page: 64 Bytes of EEPROM Program and Write: Programming (in the Flash memory block) and Writing (to the EEPROM block) and are not the same: s Flash memory bytes are programmed using the Program instruction (as shown in Table 4). This is used to change any bit values from `1's to `0's, where appropriate. As it is impossible to program bits from `0's to `1's, it is necessary to run a Sector Erase instruction before any byte overwriting can be performed.
s
EEPROM bytes are written using a simple operation (Table 3).
SDP: Software Data Protection. This is used for protecting the EEPROM block against inadvertent Write operations (for example, in noisy environments).
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M39432
Table 15. Write Mode AC Characteristics (W controlled) (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
M39432 Symbol Alt. Parameter -100 Min tAVAV tELWL3 tWLWH tDVWH tWHDX tWHEH3 tWHWL tAVWL tWLAX tGHWL tVCHEL4 tWHQV11 tWHQV21 tWHWL0 tWHGL tWHRL2,4
Note: 1. 2. 3. 4.
-120 Min 120 0 50 50 0 0 30 0 50 0 50 15 30 80 2.0 30 80 0 0 150 Max Min
-150 Max
Unit
Max
Address Valid to Next Address Valid tCS tWP tDS tDH tCH tWPH tAS tAH Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tVCS VCC High to Chip Enable Low Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Sector Erase) Time-Out between two consecutive Sector Erase tOEH tDB Write Enable High to Output Enable Low Write Enable High to Ready/Busy Output Low
100 0 50 50 0 0 30 0 50 0 50 15 2.0
150 0 65 65 0 0 35 0 65 0 50 15 2.0 30 80
ns ns ns ns ns ns ns ns ns ns s s s s ns 150 ns
0 150
Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + t Q7VQV. With a 3.3 k pull-up resistor. Chip Enable means (EE,EF) = (VIL,VIH) or (EE,EF) = (VIH,VIL). Sampled only, not 100% tested.
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M39432
Table 16. Write Mode AC Characteristics (EE or EF controlled) (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
M39432 Symbol Alt. Parameter -100 Min tWLWL tWHRH tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVCHWL tEHQV11 tEHQV21 tEHGL tEHRL2 tOEH tDB tVCS tWS tCP tDS tDH tWH tCPH tAS tAH tBLC tWC Time-out after the last byte write (EEPROM) Write Cycle Time (EEPROM) Address Valid to Next Address Valid Write Enable Low to Memory Block Enable Low Memory Block Enable Low to Memory Block Enable High Input Valid to Memory Block Enable High Memory Block Enable High to Input Transition Memory Block Enable High to Write Enable High Memory Block Enable High to Memory Block Enable Low Address Valid to Memory Block Enable Low Memory Block Enable Low to Address Transition Output Enable High to Memory Block Enable Low VCC High to Write Enable Low Memory Block Enable High to Output Valid (Program) Memory Block Enable High to Output Valid (Sector Erase) Memory Block Enable High to Output Enable Low EEPROM Block Enable High to Ready/ Busy Output Low 100 0 50 50 0 0 30 0 50 0 50 15 2.0 0 150 30 150 10 120 0 50 50 0 0 30 0 50 0 50 15 2.0 0 150 30 Max Min 150 10 150 0 65 65 0 0 35 0 65 0 50 15 2.0 0 150 30 -120 Max Min 150 10 -150 Max s ms ns ns ns ns ns ns ns ns ns ns s s s ns ns Unit
Note: 1. Time is measured to Data Polling or Toggle Bit, tWHQV = tWHQ7V + t Q7VQV. 2. With a 3.3 k pull-up resistor.
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DATA OUTPUT VALID BYTE ADDRESS (WITHIN BLOCKS) tAVQV tELQV tEHQ7V tGLQV tWHQ7V DQ7 VALID IGNORE tQ7VQV VALID DATA POLLING READ CYCLES DATA POLLING (LAST) CYCLE DATA VERIFY READ CYCLE
AI01955B
M39432
A0-A18
E
(5)
G
Figure 15. Data Polling DQ7 AC Waveforms
W
DQ7
DQ0-DQ6
LAST CYCLE OF PROGRAM OR ERASE
Note: 1. 2. 3. 4. 5.
All other timings are as a normal Read cycle. tWHQ7V is the Program or Erase time. DQ7 and DQ0-DQ6 can become valid at any point during the Data Output Valid period. During the erasing operation, the Byte address must be within the Sector being erased. E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
M39432
Table 17. Data Polling and Toggle Bit AC Characteristics 1 (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
M39432 Symbol Alt. Parameter -100 Min tWHQ7V12 tWHQ7V22 tEHQ7V12 tEHQ7V22 tQ7VQV tWHQV1 tWHQV2 tEHQV1 tEHQV2 Write Enable High to DQ7 Valid (Program, W controlled) Write Enable High to DQ7 Valid (Sector Erase, W controlled) Flash Block Enable High to DQ7 Valid (Program, EF controlled) Flash Block Enable High to DQ7 Valid (Sector Erase, EF controlled) DQ7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Sector Erase) Flash Block Enable High to Output Valid (Program) Flash Block Enable High to Output Valid (Sector Erase) 10 1.5 10 1.5 30 30 10 1.5 10 1.5 30 40 10 1.5 10 1.5 30 30 30 Max Min 10 1.5 10 1.5 30 50 10 1.5 10 1.5 30 30 30 -120 Max Min 10 1.5 10 1.5 30 55 30 -150 Max s s s s ns s s s s Unit
Note: 1. All other timings are defined in Table 13. 2. tWHQ7V is the Program or Erase time.
Table 18. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block) (TA = -40 to 85 C; VCC = 2.7 V to 3.6 V)
M39432 Parameter Min. Chip Program (Byte) Chip Erase (Pre-programmed) Chip Erase Sector Erase (Pre-programmed) Sector Erase Byte Program Program/Erase Cycles (per Sector) 100,000 Typ. 8 3 10 1 2 10 30 30 Max. s s s s s s cycles Unit
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VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE READ CYCLE
AI01956
M39432
A0-A18
E (2)
G
Figure 16. Data Toggle DQ6 AC Waveforms
W
DQ6
DQ0-DQ5, DQ7
LAST CYCLE OF PROGRAM OF ERASE
Note: 1. All other timings are as a normal Read cycle. 2. E signifies EF when EE = VIH, and it signifies EE when EF = VIH.
M39432
Figure 17. EEPROM Page Write Mode AC Waveforms (W Controlled)
A0-A14 Addr 0 Addr 1 Addr 2 Addr n
E
G tWHWL W tWLWH DQ0-DQ7 Byte 0 Byte 1 tWHRL RB
AI02028
tWLWL
tWHRH
Byte 2
Byte n
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 19. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. Table 19. Ordering Information Scheme
Example: M39432 -15 W NC 1 T
Option Speed -10 -12 -15 100 ns 120 ns 150 ns 6 Temperature Range -40 to 85 C T Tape & Reel Packing
Operating Voltage W V1 2.7 V to 3.6 V 3.0 V to 3.6 V NC Package TSOP40: 10 x 20 mm
Note: 1. The -V voltage range is no longer offered, since the -W range also covers these voltages. Similarly, products are no longer offered with a -20 or -25 marking (200 ns or 250 ns) since these are covered by the -15 (150 ns) part; and products are no longer offered with the 1 or 5 temperature ranges (0 to 70C or -20 to 85C) since these are covered by the 6 temperature range.
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M39432
Table 20. TSOP40 - 40 lead Plastic Thin Small Outline, 10 x 20 mm
mm Symbol Typ. A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 9.90 - 0.50 0 40 0.10 Min. Max. 1.20 0.15 1.05 0.27 0.21 20.20 18.50 10.10 - 0.70 5 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.390 - 0.020 0 40 0.004 Typ. Min. Max. 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.398 - 0.028 5 inches
Figure 18. TSOP40 (NC)
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: 1. Drawing is not to scale.
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M39432
Table 21. Revision History
Date 09-Oct-1998 25-Nov-1999 Document written Wider -W voltage range added, old -V range removed. Faster -10 speed range added, slowest -20 and -25 ranges removed. Narrowest temperature ranges 1 and 5 removed. Description of Revision
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M39432
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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